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p reliminary w78e378/w78c378/w78 c374 monitor controller publication release date: december 1999 - 1 - revision a1 general description the w78e378, w78c378 and w78c374b are asic which is a stand - alone high - performance microcontroller specially designed for monitor control applications. the device integrates the embedded 80c31 microcontroller core, on - chip flash or mask rom, 576 bytes of ram, and a number of dedicated hardware monitor functions. additional special function registers are incorporated to control the on - chip peripheral hardware. the chip is used to control the interface signal of other devices in the monito r and to process the video sync signals. because of the highly integration and flash cell for program memory, the device can offer users the competitive advantages of low cost and reduced development time. features 80c31 mcu core embedded 32k bytes fla sh - rom (w78e378) 32k bytes mask - rom (w78c378) 16k bytes mask - rom (w78c374b) total 576 bytes of on - chip data ram - 256 bytes accessed as in the 80c32 - 320 bytes accessed as external data memory via "movx @ri" pwm dacs - eight 8 - bit static pwm dacs : dac0 - dac8 - three 8 - bit dynamic pwm dacs: dac9 - dac10 sync processor - horizontal & vertical polarity detector - sync separator for composite sync - 12 - bit horizontal & vertical frequency counter - programmable dummy frequency generator - programmable h - clamp pulse output - soa interrupt - hsync/2 output serial ports: - ddc1 port - support ddc1 - sio1 & sio2 ports - each can support ddc2b/2b+/2bi/2ab (each has 2 slave addresses) two 16 - bit timer/counters (8031's timer0 & timer1) one external interrupt input (8031's int0 ) one parabola interrupt generator one adc with 7 multiplexed analog inputs two 12 ma(min) output pins for driving leds watchdog timer (2 22 /fosc = 0.42s @fosc = 10 mhz) power low reset frequency: 10 mhz max. (with the same p erformance as a normal 8051 that uses 20 mhz) packaged in 40/32 - pin 600 mil dip & 44 - pin plcc
p reliminary w78e378/w78c378/w78 c374 - 2 - pin configurations 40 - pin dip: w78e378e 40 - pin dip w78c378e p4.1 1 40 p4.2 W78C374E p4.0 (hfi) 2 32 - pin dip 39 p4.3 p3.5 (adc4, t0)* 3 1 3 2 38 p3.6 (adc5, t1)* p1.1 (dac1)* 4 2 31 37 p1.2 (dac2)* 32 - pin dip: w78e378 p1.0 (dac0)* 5 3 30 36 p1.3 (dac3)* w78c378 p3.4 (vout) 6 4 29 35 p1.4 (dac4)* w78c374 p3.3 (hout) 7 5 28 34 p1.5 (dac5)* h in 8 6 27 33 p1.6 (dac6)* v in 9 7 2 6 32 p1.7 (dac7)* reset 10 8 25 31 p2.0 (dac8) v dd 11 9 24 30 p2.1 (dac9) v ssa 12 10 23 29 p2.2 (dac10) oscout 13 11 22 28 p2.3 (hclamp) oscin 14 12 21 27 p2.4 (adc0) p3.2 ( int0 ) 15 13 20 26 p2.5 (adc1) p3.1 (scl)* 16 14 19 25 p2.6 (adc2) p3.0 (sda)* 17 15 18 24 p2.7 (adc3) v ss 18 16 17 23 p3.7 (adc6)* p4.7 (hfo) 19 22 p4.4 (scl2)* p4.6 20 21 p4.5 (sda2)* 44 - pin plcc h v reset v v vdda vssa oscout oscin nc p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p 3 . 1 v s s p 3 . 0 p 3 . 7 p 4 . 6 p 4 . 5 p 4 . 4 p 4 . 7 7 8 9 10 11 12 13 14 15 16 17 1 8 1 9 2 0 2 2 2 6 2 5 2 4 2 3 2 8 2 1 2 7 39 29 30 32 33 31 35 34 36 37 38 1 2 3 4 5 6 4 0 4 1 4 2 4 3 4 4 p 3 . 4 p 1 . 0 p 1 . 1 p 3 . 5 p 3 . 6 p 1 . 2 p 4 . 3 p 1 . 3 p3.2 p3.3 p 4 . 2 p 4 . 1 p 4 . 0 p1.4 p2.5 p2.4 p 2 . 7 p 2 . 6 v s s w78e378p w78c378p w78c374p dd dd in in
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 3 - revision a1 pin description pin name i/o description reset i/o chip reset input (active low) input & internal reset output (generated by wdt or power low) ttl schmitt trigger input, internal pull - up ~30 k w i ol = +12 ma @v ol = 0.45v v dd - positive power supply v s s - ground v ss - ground osc out o output from the inverting oscillator amplifier osc in i input to the inverting oscillator amplifier, 10 mhz max. h in i hsync input ttl schmitt trigger input , w/o pmos v ih /v il = 2.0v/0.8v, v+/ v - = ~1.6v/ 1.1v v in i vsy nc input ttl schmitt trigger input, w/o pmos v ih /v il = 2.0v/0.8v, v+/ v - = ~1.6v/ 1.1v p1.0 (dac0) i/o general purpose i/o, dac0 special function output open - drain output , sink current: 15 ma p1.1 (dac1) i/o general purpose i/o, dac1 special function out put open - drain output , sink current: 15 ma p1.2 (dac2) i/o general purpose i/o, dac2 special function output open - drain output , sink current: 4 ma p1.3 (dac3) i/o general purpose i/o, dac3 special function output open - drain output , sink current: 4 ma p1 .4 (dac4) i/o general purpose i/o, dac4 special function output open - drain output , sink current: 4 ma p1.5 (dac5) i/o general purpose i/o, dac5 special function output open - drain output , sink current: 4 ma p1.6 (dac6) i/o general purpose i/o, dac6 speci al function output open - drain output , sink current: 4 ma p1.7 (dac7) i/o general purpose i/o, dac7 special function output open - drain output , sink current: 4 ma
p reliminary w78e378/w78c378/w78 c374 - 4 - pin description, continued pin name i/o description p2.0 (dac8) i/o general purpose i/o, da c8 special function output sink/source current: 4 ma/ - 100 m a ( - 4 ma for sf output) p2.1 (dac9) i/o general purpose i/o, dac9 special function output sink/source current: 4 ma/ - 100 m a ( - 4 ma for sf output) p2.2 (dac10) i/o general purpose i/o, dac10 speci al function output sink/source current: 4 ma/ - 100 m a ( - 4 ma for sf output) p2.3 (hclamp) i/o general purpose i/o, hclamp special function output sink/source current: 4 ma/ - 100 m a ( - 4 ma for sf output) p2.4 (adc0) i/o general purpose i/o, adc input channe l 0 sink/source current: 4 ma/ - 100 m a p2.5 (adc1) i/o general purpose i/o, adc input channel 1 sink/source current: 4 ma/ - 100 m a p2.6 (adc2) i/o general purpose i/o, adc input channel 2 sink/source current: 4 ma/ - 100 m a p2.7 (adc3) i/o general purpose i /o, adc input channel 3 sink/source current: 4 ma/ - 100 m a p3.0 (sda) i/o general purpose i/o, ddc port serial data i/o schmitt trigger input v ih /v il = 0.7 v dd /0.3 v dd , v+/v - = ~0.6 v dd / 0.4 v dd open - drain output , sink current: 8 ma p3.1 (scl) i/o general purpose i/o, ddc port serial clock i/o schmitt trigger input v ih /v il = 0.7 v dd /0.3 v dd , v+/v - = ~0.6 v dd / 0.4 v dd open - drain output , sink current: 8 ma p3.2 ( int0 ) i/o general purpose i/o, int0 input sink/source curr ent: 1 ma/ - 100 m a p3.3 (h out ) i/o general purpose i/o, h out special function output sink/source current: 4 ma/ - 100 m a ( - 4 ma for sf output) p3.4 (v out ) i/o general purpose i/o, v out special function output sink/source current: 4 ma/ - 100 m a ( - 4 ma for sf output) p3.5 (adc4, t0) i/o general purpose i/o, adc input channel 4 open - drain output , sink current: 4 ma p3.6 (adc5, t1) i/o general purpose i/o, adc input channel 5 open - drain output , sink current: 4 ma p3.7 (adc6) i/o general purpose i/o, adc input channel 6 open - drain output , sink current: 4 ma
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 5 - revision a1 pin description, continued pin name i/o description p4.0 (hfi) i/o p4.0 output, hfi input sink/source current: 4 ma/ - 4 ma p4.1 o p4.1 output sink/source current: 4 ma/ - 4 ma p4.2 o p4.2 output sink/sour ce current: 4 ma/ - 4 ma p4.3 o p4.3 output sink/source current: 4 ma/ - 4 ma p4.4 (scl2) i/o p4.4 output, sio2 port serial clock i/o schmitt trigger input v ih /v il = 0.7 v dd /0.3 v dd , v+/v - = ~0.6 v dd /0.4 v dd open - drain output , sink current: 8 ma p4.5 (sda2 ) i/o p4.5 output, sio2 port serial data i/o schmitt trigger input v ih /v il = 0.7 v dd /0.3 v dd , v+/v - = ~0.6 v dd /0.4 v dd open - drain output , sink current: 8 ma p4.6 o p4.6 output sink/source current: 4 ma/ - 4 ma p4.7 (hfo) o p4.7 output, hfo output sink/sour ce current: 4 ma/ - 4 ma
p reliminary w78e378/w78c378/w78 c374 - 6 - block diagram cpu osc. circuit reset circuit power low detection int0 (p3.2) interrupt processor timer 0 timer 1 oscin oscout 80c31 core excluding internal ram adc adc0 (p2.4) adc1 (p2.5) adc2 (p2.6) adc3 (p2.7) adc4 (p3.5) adc5 (p3.6) adc6 (p3.7) vpp (p3.2) v v 8-bit internal bus watch dog timer sync. processor p4 i/o port static dacs dynamic dacs dac0~7 (p1.0~p1.7) dac8~10 (p2.0~p2.2) sio1 scl (p3.1) sda (p3.0) reset program memory ram: 576 bytes data memory t0 (p3.5) t1 (p3.6) note: p1, p4.4~p4.5 p3.0~p3.1 & p3.5~p3.7 are open-drain. note: freq1 = freq2 freq1 freq2 p1, p2, p3 sio2 scl2 (p4.4) sda2 (p4.5) hin, vin hfi (p4.0) vout (p3.4) hout (p3.3) hclamp (p2.3) hfo (p4.7) dd ss
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 7 - revision a1 functional descripti on address space direct addressing "mov" indirect addressing "mov @ri" internal ram 256 bytes 8051sfrs & serial ports sfrs internal program memory external access "movx @ri" on-chip data memory 128 bytes 00h 80h ffh 00h direct or indirect addressing "mov" or "mov @ri" new sfrs 80h external access "movx @ri" 0000h external access "movx @ri" on-chip data memory 64 bytes c0h on-chip data memory 128 bytes 00h external access "movx @ri" bank0 bank1 ffh 7fh 7fh 7fh bfh 7fffh external access "movx @ri" (3fffh) program/data/sfrs address space sfrs accessed using 'direct addressing' register address bits power on reset reset r/w 1 a* e0h 8 00h 00h r/w 2 b* f0h 8 00h 00h r/w 3 psw* d0h 8 00h 00h r/w 4 sp 81h 8 00h 00h r/w 5 dpl 82h 8 00h 00h r/w 6 dph 83h 8 00h 00h r/w 7 ie* a8h 8 00h 00h r/w 8 ip* b8h 8 00h 00h r/w 9 tcon* 88h 8 00h 00h r/w 10 tmod 89h 8 00h 00h r/w 11 tl0 8ah 8 00h 00 h r/w 12 th0 8ch 8 00h 00h r/w 13 tl1 8bh 8 00h 00h r/w 14 th1 8dh 8 00h 00h r/w 15 pcon 87h 8 00h x0h r/w
p reliminary w78e378/w78c378/w78 c374 - 8 - sfrs accessed using 'direct addressing', continued register address bits power on reset reset r/w 16 p1* 90h 8 00h 00h r/w 17 p2* a0h 8 ffh ffh r/w 18 p3* b0h 8 1fh 1fh r/w 19 tmreg* c0h 3 00h xxh r/w 20 s1con* d8h 8 00h 00h r/w 21 s1sta d9h 8 f8h f8h r 22 s1dat dah 8 ffh ffh r/w 23 s1adr1 dbh 8 00h 00h r/w 24 s1adr2 dch 8 00h 00h r/w 25 s2con* e8h 8 00h 00h r/w 26 s2sta e9h 8 f8h f8 h r 27 s2dat eah 8 ffh ffh r/w 28 s2adr1 ebh 8 00h 00h r/w 28 s2adr2 ech 8 00h 00h r/w notes: 1. the sfrs marked with an asterisk (*) are both bit - and byte - addressable. 2. port 1 and p3.5 - p3.7 outputs low during & after reset. 3. "x" means no reset ac tion. 4. the sfrs in the shaded region are new - defined. * modified pcon bit name function 0 adcs2 adc channel select bit 2 1 pd power down bit 2 gf0 general purpose flag bit 3 gf1 general purpose flag bit 4 test0 test purpose flag bit 5 test1 test pu rpose flag bit 6 adccal set 0/1 to select 1.0v/3.0v for adc calibration 7 cpuhalt set to let cpu halt when the chip runs internally * tmreg : test mode register bit name function 0 tm1 test mode1 1 tm2 test mode2 2 tm3 test mode3
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 9 - revision a1
p reliminary w78e378/w78c378/w78 c374 - 10 - sfrs accessed usin g 'movx @ri' register address bits power on reset reset r/w type 1 ctrl1 80h 8 00h 00h w 2 ctrl2 81h 8 00h 00h w 3 p1sf 82h 8 00h xxh w 4 p2sf 83h 8 00h xxh w 5 p3sf 84h 8 00h 00h w 6 paral 85h 8 00h 00h r/w 7 parah 86h 5 00h 00h r/w 8 hfcountl 8 7h 8 x x r 9 hfcounth 88h 8 x x r 10 vfcountl 89h 8 x x r 11 vfcounth 8ah 8 x x r 12 wdtclr 8bh - x x w 13 soarl 8ch 8/6 x x r/w 14 soarh 8dh 8/6 x x r/w 15 soaclr 8eh - x x w 16 intmsk 8fh 6 00h 00h r/w 17 intvect 90h 6 00h 00h r 18 intclr 91h 6 x x w 19 ddc1 92h 8 x x w 20 adc 93h 8 x x r 21 dac0 94h 8 00h x r/w 22 dac1 95h 8 00h x r/w 23 dac2 96h 8 00h x r/w 24 dac3 97h 8 00h x r/w 25 dac4 98h 8 00h x r/w 26 dac5 99h 8 00h x r/w 27 dac6 9ah 8 00h x r/w 28 dac7 9bh 8 00h x r/w 29 dac8 9ch 8 00h x r/w 30 dac9 9dh 8 00h x r/w 31 dac10 9eh 8 00h x r/w 32 p4 9fh 8 ffh ffh w 33 ctrl3 a0h 0 00h 00h w note: "x" means no reset action.
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 11 - revision a1 * ctrl1 : control register 1 (write only) bit name function 0 adcstrt a - to - d conversion start control s et by s/w to start conversion. cleared by h/w while conversion completed (read soarh.6 to check). 1 adcs0 adc channel select bit 0 2 adcs1 adc channel select bit 1 3 enddc1 enable ddc1 4 hces h - clamp edge select 0: select leading edge of restored hsync 1: select trailing edge of restored hsync 5 hcws h - clamp width select bit 6 dummyen dummy signal enable 7 vsdis vsync separator disable, 0: enable, 1: disable * ctrl2 : control register 2 (write only) bit name function 0 hsps hsync polarity select 0: positive, 1: negative 1 vsps vsync polarity select 0: positive, 1: negative 2 hdums0 h dummy frequency select 0 3 vdums v dummy frequency select 4 ddc1b9 bit 9 in ddc1 mode 5 wdten enable watch dog timer 6 soahdis disable soa low to high detection 7 oschi osc freq. higher than 10 mhz * ctrl3 : control register 3 (write only) bit name function 0 enhfo enable hf input/output for p4.0/p4.7, respectively 0: disable, 1: enable 1 hdums1 h dummy frequency select 1 2 hfo_pol select hfo polarity 0: positi ve, 1: negative
p reliminary w78e378/w78c378/w78 c374 - 12 - 3 hfo_half select hfo output freq. 0: the same as hfi, 1: half of the hfi 4 enbnk1 select on - chip ext. ram bank 0: bank 0, 1: bank 1 5 - 7 - - *p1sf : port1 special function output enable register (write only) bit name function 0 p10sf po rt 1.0 special function enable (dac0 output) 1 p11sf port 1.1 special function enable (dac1 output) 2 p12sf port 1.2 special function enable (dac2 output) 3 p13sf port 1.3 special function enable (dac3 output) 4 p14sf port 1.4 special function enable ( dac4 output) 5 p15sf port 1.5 special function enable (dac5 output) 6 p16sf port 1.6 special function enable (dac6 output) 7 p17sf port 1.7 special function enable (dac7 output) *p2sf : port2 special function output enable register (write only) bit name function 0 p20sf port 2.0 special function enable (dac8 output) 1 p21sf port 2.1 special function enable (dac9 output) 2 p22sf port 2.2 special function enable (dac10 output) 3 p23sf port 2.3 special function enable (hclamp output) 4 p24sf port 2.4 s pecial function enable (adc0 input) 5 p25sf port 2.5 special function enable (adc1 input) 6 p26sf port 2.6 special function enable (adc2 input) 7 p27sf port 2.7 special function enable (adc3 input) *p3sf : port3 special function output enable register ( write only) bit name function 0 - 2 - - 3 p33sf port 3.3 special function enable (h out ) 4 p34sf port 3.4 special function enable (v out ) 5 - 7 - - *hfcountl : horizontal frequency counter register, low byte (read only) bit name function 0 hf0 h frequency count bit 0 1 hf1 h frequency count bit 1 2 hf2 h frequency count bit 2
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 13 - revision a1 3 hf3 h frequency count bit 3 4 hf4 h frequency count bit 4 5 hf5 h frequency count bit 5 6 hf6 h frequency count bit 6 7 hf7 h frequency count bit 7 *hfcounth : horizontal freq uency counter register, high byte (read only) bit name function 0 hf8 h frequency count bit 8 1 hf9 h frequency count bit 9 2 hf10 h frequency count bit 10 3 hf11 h frequency count bit 11 4 - 5 - - 6 noh set by hardware if no hin signal 7 hpol hin pol arity. 0: positive, 1: negative *vfcountl : vertical frequency counter register, low byte (read only) bit name function 0 vf0 v frequency count bit 0 1 vf1 v frequency count bit 1 2 vf2 v frequency count bit 2 3 vf3 v frequency count bit 3 4 vf4 v fre quency count bit 4 5 vf5 v frequency count bit 5 6 vf6 v frequency count bit 6 7 vf7 v frequency count bit 7 *vfcounth : vertical frequency counter register, high byte (read only) bit name function 0 vf8 v frequency count bit 8 1 vf9 v frequency count bit 9 2 vf10 v frequency count bit 10 3 vf11 v frequency count bit 11 4 - 5 - - 6 nov set by hardware if no v in signal 7 vpol v in polarity. 0: positive, 1: negative * intvect : interrupt vector register (read only) bit name function 0 sclint scl pin p ulled low detected 1 adcint adc conversion completed
p reliminary w78e378/w78c378/w78 c374 - 14 - 2 ddc1int ddc1 port buffer empty 3 soaint soa condition happen 4 vevent vsync pulse detected or nov = 1 (v counter overflow) (the vevent is designed to be generated only 'one' time if no vsync input. ) 5 paraint parabola interrupt generated * intmsk : interrupt mask register (read/write) bit name function 0 msclint set/clear to enable/disable sclint 1 madcint set/clear to enable/disable adcint 2 mddc1int set/clear to enable/disable ddc1int 3 msoai nt set/clear to enable/disable soaint 4 mvevent set/clear to enable/disable vevent 5 mparaint set/clear to enable/disable paraint * intclr (write only) bit name function 0 csclint write 1 to this bit to clear sclint in intvect 1 cadcint write 1 to thi s bit to clear adcint in intvect 2 cddc1int write 1 to this bit to clear ddc1int in intvect 3 csoaint write 1 to this bit to clear soaint in intvect 4 cvevent write 1 to this bit to clear vevent in intvect 5 cparaint write 1 to this bit to clear parain t in intvect *paral : parabola interrupt generator register, low byte (read/write) bit name function 0 para0 paraint period register bit 0 1 para1 paraint period register bit 1 2 para2 paraint period register bit 2 3 para3 paraint period register bit 3 4 para4 paraint period register bit 4 5 para5 paraint period register bit 5 6 para6 paraint period register bit 6 7 para7 paraint period register bit 7 *parah : parabola interrupt generator register, high byte (read/write) bit name function
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 15 - revision a1 0 para8 p araint period register bit 8 1 para9 paraint period register bit 9 2 para10 paraint period register bit 10 3 para11 paraint period register bit 11 4 para12 paraint period register bit 12
p reliminary w78e378/w78c378/w78 c374 - 16 - *soarl : soa register, low byte (read/write) bit name function 0 sl0 soa low register bit 0 1 sl1 soa low register bit 1 2 sl2 soa low register bit 2 3 sl3 soa low register bit 3 4 sl4 soa low register bit 4 5 sl5 soa low register bit 5 6 (ovl) ovl = 1: current h count larger than soarl, for test 7 (ovh) ovh = 1: current h count smaller than soarh, for test *soarh : soa register, high byte (read/write) bit name function 0 sh0 soa high register bit 0 1 sh1 soa high register bit 1 2 sh2 soa high register bit 2 3 sh3 soa high register bit 3 4 sh4 soa high reg ister bit 4 5 sh5 soa high register bit 5 6 (adcstrt) adcstrt bit status, for test 7 (wdtq10) watch dog timer, bit 10, for test * adc result of the a - to - d conversion. * dac0 ~ dac8 8 - bit pwm static dac register. * dac9 ~ dac10 8 - bit pwm dynamic dac regi ster. * wdtclr watchdog - timer - clear register, without real hardware but an address. writing any value to wdtclr will clear the watchdog timer. * soaclr safe - operation - area clear register, without real hardware but an address. writing any value to soaclr will clear the soaint. * ddc1 ddc1 latch buffer. * s1con sio1 control register. * s1sta sio1 status register. * s1dat sio1 data register. * s1adr1, s1adr2 sio1 address registers. * s2con sio2 control register. * s2sta sio2 status register. * s2dat sio2 data register.
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 17 - revision a1 * s2adr1, s2adr2 sio2 address registers.
p reliminary w78e378/w78c378/w78 c374 - 18 - modified timer 0 & timer 1 osc 6 . . tr0 gate int0 pin (p3.2) t0 pin (p3.5) c/t = 0 c/t = 1 modified point in timer 0 (not divided by 12) to tl0 osc 6 . . tr1 gate t1 pin (p3.6) c/t = 0 c/t = 1 modified point in timer 1 (not divided by 12) to tl1 v modified point in timer 1 (no int1 pin) dd
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 19 - revision a1 ddc1/sio1 and sio2 ports 1. ddc1/sio1 port ddc1 enddc1 ddc port scl sda sio1 support ddc2b/2b+ support ddc1 in in out out out scl sda sda scl 0 1 vsync enddc1 = 1, used as ddc 1 (display data channel) port: to support ddc1, use vsync signal for shift clock and p3.0 (sda) for data output. enddc1 = 0, used as sio1 port: to support ddc2b/2b+/2bi/2ab, use p3.1 (scl) for serial clock and p3.0 (sd a) for serial data. sclint interrupt is generated when scl (p3.1) has a high - to - low transition and then keeps at low for 16 1/fosc. fosc 8 mhz 10 mhz scl low 2 m s 1.6 m s 2. sio2 port: to support ddc2b/2b+/2bi/2ab, use p4.4 (scl) for serial clock and p4.5 (sda) for serial data. ddc1 port the ddc1 is a serial output port that supports ddc1 communication. to enable the ddc1 port, enddc1 (bit 3 of ctrl1) should be set to '1'. once previous eight data bits in the shift regi ster and one null bit (the 9th bit) are shifted out to the sda sequentially on each rising edge of the v in signal, the ddc1 control circuit loads the next data byte from the latch buffer (the ddc1 register) to the shift register and generates a ddc1int sig nal to the cpu. in the interrupt service routine, the s/w should fetch the next byte of edid data and write it to the ddc1 register. if enddc1 is cleared, the shift register is stopped, and the sda output is kept high. the bit ddc1b9 (bit 4 of ctrl2) decid es the 9th bit in a ddc transmission. if ddc1b9 is set, the 9th bit will be '1', otherwise '0'.
p reliminary w78e378/w78c378/w78 c374 - 20 - to use ddc1 port, a user should pay attention to the following items: (1) when the chip is powered - on or after reset , the 8 - bit shift register in ddc1 h/w contai ns all 0s. if you write a data to the latch buffer (the ddc1 register), it will be loaded to the shift register at the 9th clock (on v in ), so from the 10th clock, the real data bit begins to shift out. (2) because there is no reset signal to the latch buffer, it contains a random data after power - on. if you enable ddc1 without writing data to the latch buffer, sda will have the random data shifted out after 9 clocks. the shift register is reset to 00h during cpu reset. (3) the ddc1 h/w has a counter that counts how many bits shifted out. this counter is initialized to 0 when power - up or reset. when you firstly enable ddc1 after power - on, the first bit is already shifted out without clock, so the first clock triggers the second data bit (d6) to shift out and "0000 00 01 1" will be got. after the first 9 clocks that shift out an invalid byte, the counter counts from 1 to 9 cyclically according to the clock pulse on v in - pin. see the following illustration. after power on, the counter count: 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ... shifted - out data bit: 0 0 0 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack ? v in clock pulse: 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ... | -- > invalid data | -- > normal data (4) the interrupt happens on the failing edge of the following first clock. the next data, which is about to be shifted out, in the latch buffer is loaded into the shift register at the rising edge of the following first clock. at the same time, data bit d7 is shifted out and the counter value is "1". sio1 port (with two slave addresses) the sio1 port is a serial i/o port, which suppo rts all transfer modes from and to the i 2 c bus. the sio1 port handles byte transfers autonomously. to enable this port, the bit enddc1 in ctrl1 should be cleared to '0'. the cpu interfaces to the sio1 port through the following five special function regist ers: s1con (control register, d8h), s1sta (status register, d9h), s1dat (data register, dah) and s1adr1 / s1adr2 (address registers, dbh/dch). the sio1 h/w interfaces to the i 2 c bus via two pins: sda (p3.0, serial clock line) and scl (p3.1, serial data line) . the output latches of p3.0 and p3.1 must be set to "1" before using this port. sio2 port (with two slave addresses) the function of this port is the same as sio1 port. the cpu interfaces to the sio2 port through the following five special function regist ers: s2con (control register, e8h), s2sta (status register, e9h), s2dat (data register, eah) and s2adr1 / s2adr2 (address registers, ebh/ech). the sio2 h/w interfaces to the i 2 c bus via two pins: sda2 (p4.5, serial clock line) and scl2 (p4.4, serial data lin e). the output latches of p4.5 and p4.4 must be set to "1" before using this port. operation of sio1 port: (sio2 has the same function except their addresses of control registers)
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 21 - revision a1 a) control registers a - 1) the address registers, s1adr1, s1adr2 the sio1 is equipped with two address registers: s1adr1 & s1adr2. the cpu can read from and write to these two 8 - bit, directly addressable sfrs. the content of these registers are irrelevant when sio1 is in master modes. in the slave modes, the seven most significant bits must be loaded with the mcu's own address. the sio1 hardware will react if either of the addresses is matched. 7 6 5 4 3 2 1 0 x x x x x x x - | ------------------------ own slave address ----------------------- | a - 2) the data register, s1dat this r egister contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from or write to this 8 - bit directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag (si) is set. data in s1dat remains stable as long as si is set. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in t he event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. 7 6 5 4 3 2 1 0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 |< ---------------------------- shift direction ----------------------------- s 1dat and the acknowledge bit form a 9 - bit shift register, the acknowledge bit is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the acknowledge bit into s1dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit (ack or nack) is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat on the falling edges of scl clock pulses, and is shifted into s1dat on the rising edges of scl clock pulses. a - 3) the control register, s1con the cpu can read from and write to this 8 - bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set wh en a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the bus. the sto bit is also cleared when ens1 = "0". 7 6 5 4 3 2 1 0 cr2 ens1 sta sto si aa cr1 cr0 ens1, the sio1 enable bit ens1 = "0": when ens1 is "0" , the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio1 is in the not addressed slave state, and sto bit in s1con is forced to "0". no other bits are affected. p3.0 (sda) and p3.1 (scl) may be used as open drain i/o ports. ens1 = "1": when ens1 is "1", sio1 is enabled. the p3.0 and p3.1 port latches must be set to logic 1.
p reliminary w78e378/w78c378/w78 c374 - 22 - sta, the start flag sta = "1": when the sta bit is set to enter a master mode, the sio1 hardware checks the status of i2c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop condition and generates a start condition after a delay. if sta is set while sio1 is already in a master mode and one or more bytes are transmitted or received, sio1 tr ansmits a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = "0": when the sta bit is reset, no start condition or repeated start condition will be generated. sto, the stop flag sto = "0": when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i2c bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an bus error condition. in this case, no stop condition is transmitted to the i2c bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the defined not addressed slave receiver mode. the sto flag is automatically cleared by ha rdware. if the sta and sto bits are both set, then a stop condition is transmitted to the i2c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. si, the serial interrupt flag si = "1": when a new sio1 state is present in the s1sta register, the si flag is set by hardware, and, if the ea and es bits (in ie register) are both set, a serial interrupt is requested. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. when si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the s erial interrupt flag. si must be cleared by software. si = "0": when the si flag is reset, no serial interrupt is requested, and there is no stretching on the serial clock on the scl line. aa, the assert acknowledge flag aa = "1": if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: 1) the own slave address has been received. 2) a data byte has been received while sio1 is in the master receiver mode. 3) a data byte has been receiv ed while sio1 is in the addressed slave receiver mode. aa = "0": if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: 1) a data has been received while sio1 is in the master receive r mode. 2) a data byte has been received while sio1 is in the addressed slave receiver mode. cr0, cr1 and cr2, the clock rate bits these three bits determine the serial clock frequency when sio1 is in a master mode. it is not important when sio1 is in a sl ave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100 khz.
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 23 - revision a1 bit freq. (khz) @fosc cr2 cr1 cr0 8 mhz 10 mhz fosc divided by 0 0 0 31.25 39.1 256 0 0 1 35.7 44.6 224 0 1 0 41.7 52.1 192 0 1 1 50.0 62. 5 160 1 0 0 8.3 10.4 960 1 0 1 66.7 83.3 120 1 1 0 133.3 166.7 60 a - 4) the status register, s1sta s1sta is an 8 - bit read - only register. the three least significant bits are always 0. the five most significant bits contain the status code. there are 23 possible status codes. when s1sta contains f8h , no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is present in s 1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. in addition, state 00h stands for a bus error. a bus error occurs when a start or stop condition is present at an illegal positio n in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. b) operating modes the four operating modes are: master/transmitter, master/receiver, slave/transmitter and slave/rec eiver. bits sta, sto and aa in s1con decide the next action the sio1 hardware will take after si is cleared. when the next action is completed, a new status code in s1sta will be updated and si will be set by hardware in the same time. now, the interrupt s ervice routine is entered (if the si_interrupt is enabled), the new status code can be used to decide which appropriate service routine the software is to branch. data transfers in each mode are shown in the following figures. *** legend for the following four figures:
p reliminary w78e378/w78c378/w78 c374 - 24 - (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack bit will be received. sla+w has been transmitted; ack has been received. 18h 08h a start has been transmitted. last action is done last state next setting in s1con expected next action new state next action is done 1) "data byte will be transmitted": software should load the data byte (to be transmitted) into s1dat before new s1con setting is done. 2) "sla+w (r) will be transmitted": software should load the sla+w/r (to be transmitted) into s1dat before new s1con setting is done. 3) "data byte will be received": software can read the received data byte from s1dat while a new state is entered. software's access to s1dat with respect to "expected next action":
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 25 - revision a1 (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack bit will be received. master/transmitter mode from master/receiver (b) set sta to generate a start. sla+w has been transmitted; ack has been received. 18h 20h sla+w has been transmitted; not ack has been received. or 28h data byte in s1dat has been transmitted; ack has been received. data byte in s1dat has been transmitted; not ack has been received. 30h or (sta,sto,si,aa)=(0,0,0,x) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted. (sta,sto,si,aa)=(0,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(1,1,0,x) to master/receiver (a) (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be received; sio1 will be switched to mst/rec mode. send a stop send a stop followed by a start 38h arbitration lost in sla+r/w or data bytes. (sta,sto,si,aa)=(0,0,0,x) i2c bus will be released; not addressed slv mode will be entered. (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted when the bus becomes free. enter naslave send a start when bus becomes free 08h a start has been transmitted. 10h a repeated start has been transmitted. from slave mode (c) a stop will be transmitted; sto flag will be reset.
p reliminary w78e378/w78c378/w78 c374 - 26 - master/receiver mode (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack will be received. 50h data byte has been received; ack has been returned. sla+r has been transmitted; ack has been received. 40h from master/transmitter (a) to master/transmitter (b) 58h data byte has been received; not ack has been returned. sla+r has been transmitted; not ack has been received. 48h set sta to generate a start. 08h a start has been transmitted. 38h arbitration lost in not ack bit. (sta,sto,si,aa)=(0,0,0,x) i2c bus will be released; not addressed slv mode will be entered. enter naslave (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted when the bus becomes free. send a start when bus becomes free (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack will be received; sio1 will be switched to mst/trx mode. (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted. (sta,sto,si,aa)=(0,1,0,x) a stop will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. send a stop send a stop followed by a start from slave mode (c)
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 27 - revision a1 slave/transmitter mode a8h own sla+r has been received; ack has been returned. b0h arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned. or c8h last data byte in s1dat has been transmitted; ack has been received. b8h data byte in s1dat has been transmitted; ack has been received. c0h data byte or last data byte in s1dat has been transmitted; not ack has been received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,0) last data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,0) last data byte will be transmitted; ack will be received. set aa (sta,sto,si,aa)=(1,0,0,1) switch to not addressed slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. ` enter naslave send a start when bus becomes free to master mode (c)
p reliminary w78e378/w78c378/w78 c374 - 28 - 88h previously addressed with own sla address; data has been received; not ack has been returned. 60h own sla+w has been received; ack has been returned. 68h arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned. or slave/receiver mode a0h a stop or repeated start has been received while still addressed as slv/rec. 80h previously addressed with own sla address; data has been received; ack has been returned. (sta,sto,si,aa)=(0,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. set aa (sta,sto,si,aa)=(1,0,0,1) switch to not addressed slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. ` enter naslave send a start when bus becomes free to master mode (c) (sta,sto,si,aa)=(0,0,0,1) data will be received; ack will be returned.
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 29 - revision a1 parabola interrupt generator the parabola interrupt generator is a 13 - bit auto - reload timer, which generates an interrupt to the cpu periodi cally for software to load the parabola waveform data to the dynamic dacs (dac8 - dac10). the software should calculate the value of the parah and paral registers by: (vcount 16) ? segment number . the segment number is the number of integration segments be tween two vsync pulses. the interrupt interval is programmable: time base = 1/fosc programmable interrupt period = time base (parah 256 + paral + 1) maximum period = time base 8192 note: zero value in [parah, paral] is inhibited. a - to - d converter (ref. application note in appendix a.) one 4 - bit analog - to - digital converter. conversion time = (6/fosc) 128 sec. 7 channels selected by an analog multiplexer (adcs2, adcs1, adcs0) (0, 0, 0) (0, 0, 1) (0, 1, 0) (0, 1, 1) (1, 0, 0) (1, 0, 1) (1, 1, 0) selected channel adc0 adc1 adc2 adc3 adc4 adc5 adc6 the convers ion of the adc is started by setting bit adcstrt in ctrl1 by software. when the conversion is completed, the adcstrt bit is cleared by hardware automatically, and the adcint bit in intvect is set by hardware at the same time if madcint in intmsk is set. p wm dacs eight 8 - bit static dacs: dac0 - dac7 the pwm frequency f pwm = fosc 255 the duty cycle of the pwm output = register value 255 the dc voltage after the low pass filter = v cc duty cycle static dac application circuit: static dac low-pass filter v output r c t = rc v output = v cc ??n/255, if t >> t pwm
p reliminary w78e378/w78c378/w78 c374 - 30 - three 8 - bit dynamic dacs: dac8 - dac10 the dynamic dacs are especially used to generate parabola waveform for geometric compensation, or to be used as static dacs. dyn amic dac application circuit: dynamic dac v output 100k 470 +vsync 0.022u 10u/50v 470 470 10k 10k 4.7u/16v vdd the following types of distoration can be compensated: 1. h size distortion: a. pincushion correction (amplitude) b. trapezoid (keystone) c. cbow (quarter width) 25% 25% d. pincushion correction (corner) e. s curve the pcc amplitude can be compensated against v size adjustment automatically. the trapzoid can be compensated against v center adjustment automatically. 2. h center distortion: a. pin balance (bow) b. key balance (tilt) c. corner bal ance
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 31 - revision a1 sync processor polarity detector the h/v polarity is detected automatically and can be known from hpol bit (hfcounth.7) and vpol bit (vfcounth.7). fosc 10 mhz max. h+v width (64/fosc) 62 (counter over flow) = 396.8 m s max. v width (2048/fosc) 2 = 409.6 m s sync separator the vsync is separated from the composite sync automatically, without any software effort. fosc 10 mhz min. v width & max. h width (1/fosc) 64 = 6.4 m s horizontal & vertical freq uency counter there are two 12 - bit counters which can count h and v frequency automatically. when vevent (vsync frequency counter timeout) interrupt happens, the count value values are latched into the counter registers (hfcounth, hfcountl, vfcounth and vf countl). and then the s/w may read the count value (h count and v count ) from the counter registers to calculate the h and v frequency by the formulas listed below. v frequency: the resolution of v frequency counter: v resol = (1/fosc) 64. the v frequency: v freq = 1/(v count v resol ). the lowest v frequency can be detected: fosc 262144. (38.1hz @fosc =10 mhz) h frequency: the resolution of h frequency counter: h resol = (1/fosc) ? 8. the h frequency: h freq = 1/(h count h resol ). the lowest h frequency can b e detected: fosc ? 512. (19.5 khz @fosc = 10 mhz) dummy frequency generator the dummy h and v frequencies are generated for factory burn - in or showing warning message while there are no input frequency. (hdums1, hdums0) (0, 0) (0, 1) (1, 0) (1, 1) f dummyh fosc/(8 4 8) fosc/(8 2 8) fosc/(8 3 8) fosc/(8 5 8) hsync width (8 4)/fosc (8 2)/fosc (8 3)/fosc (8 5)/fosc vdums 0 1 f dummyv f dummyh / 512 f dummyh /1024 vsync width 8/ f dummyh 16/ f dummyh
p reliminary w78e378/w78c378/w78 c374 - 32 - hdummy ..... ..... ..... ..... ..... ..... vdummy vsync width hsync width 1/fdummyh 1/fdummyv for fosc = 10 mhz: (hdums1, hdums0) (0, 1) (1, 0) (0, 0) (1, 1) f dummyh 78.125 khz 52.083 khz 39.063 khz 31.250 khz hsync width 1.6 m s 2.4 m s 3.2 m s 4.0 m s vdums 0 1 0 1 0 1 0 1 f dummyv 152.6 hz 76.3 hz 101.7 hz 50.9 hz 76.3 hz 38.1 hz 61.0 hz 30.5 hz h - clamp pul se generator 1. leading edge/trailing edge selectable. * hces = 0: select leading edge * hces = 1: select trailing edge negative polarity hsync postive polarity hsync (leading-edge) (trailing-edge) (leading-edge) (trailing-edge) hclamp hsync hsync hclamp hclamp hclamp
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 33 - revision a1 2. pulse width selectable. for fosc = 10 mhz: hcws = 0 hcws = 1 pulse width 500 - 600 ns 900 - 1000 ns saf e operation area (soa) interrupt upper boundary frequency = f osc / [8 soarh] lower boundary frequency = f osc / [8 (soarl + 1)] function description: if the condition, h freq lower than the lower boundary freq. or higher than the upper boundary freq., h appens twice continuously, the soaint will be activated. if the hin is stopped for a certain period, the soaint will also be generated. the no hsync response time is 512/f osc . (e.x., 51.2us for 10 mhz) if soahdis = 1, then no upper boundary frequency. half hsync output when enhfo (bit 0 of ctrl3) is set, p4.7 (hfo) will output the same or half frequency from p4.0 (hfi). the divide - by - two operation is done at the falling edge of hfi signal when hfo_half (bit 3 of ctrl3) is set. the polarity of hfo is sp ecified by hf_pol (bit 2 of ctrl3). hfi hfo (hfo_half=0) (hf_pol=1) hfo (hfo_half=0) (hf_pol=0) hfo (hfo_half=1)
p reliminary w78e378/w78c378/w78 c374 - 34 - interrupts the five interrupt sources are listed as below. source vector address descripton priority within a le vel 1 ie0 0003h interrupt 0 edge detected highest 2 tf0 000bh timer 0 overflow 3 ie1 0013h miscellaneous interrupts *1 4 tf1 001bh timer 1 overflow 5 si1+si2 002bh sio1 or sio2 interrupt lowest note: *1: sclint + adcint + ddc1int + soaint + vevent + paraint. the miscellaneous interrupts at vector address 0013h is driven by the f ollowing six sources, which are: (1) sclint: when high - to - low transition on scl - pin, (2) adcint: when a - to - d conversion completion, (3) ddc1int: when ddc1 data byte transmitted (after 9 clock pulses from v in ) in the ddc port, (4) soaint: when soa activated , (5) vevent: on every vsync pulse or vertical frequency counter overflow, (6) paraint: when parabola timer timeout. if ie1 interrupt occurs, it is necessary for the programmer to read the intvect register to tell where the interrupt request comes. these sources can be masked individually by clearing their corresponding bits in the intmsk register. to clear any of these interrupt flags, just write a '1' to the corresponding bit in the intclr. the interrupt enable bits and priority control bits for these f ive main sources are listed as below. interrupt flag enable bit priority control bit 1 ie0 ie.0 & ie.7 ip.0 2 tf0 ie.1 & ie.7 ip.1 3 ie1 ie.2 & ie.7 ip.2 4 tf1 ie.3 & ie.7 ip.3 5 si+si2 ie.5 & ie.7 ip.5
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 35 - revision a1 bit 0 bit 1 bit 4 bit 3 bit 2 ie1 it1 0 1 scl interrupt adc interrupt ddc1 interrupt soa interrupt vevent interrupt para interrupt intmsk intvect sclint adcint ddc1int vevent soaint paraint bit 5 0 2 1 3 4 5 ie0 tf0 tf1 ie 0013h 001bh 002bh 000bh 0003h ie.3 ie.5 ie.2 ie.1 ie.0 ie.7 ip ip.0 ip.1 ip.2 ip.3 ip.5 vector address high priority low priority interrupt polling sequence ie1 si1+si2
p reliminary w78e378/w78c378/w78 c374 - 36 - reset circuit - power - l ow detector & watchdog timer the reset signals come from the following three sources: 1. external reset input (active low) 2. power low detect 3. hardware watchdog timer the power - low detection circuit generates a reset signal once the v cc falls below 3 .5v for above 10 m s or falls below 1.8v , and the reset signal is released after v cc goes up to 4.3v . 4.3v 3.8v 1.8v vcc power-low reset 10us the purpose of a watchdog timer is to reset the cpu if the user program fails to reload the watchdog timer within a reasonable peri od of time known as the "watchdog interval". the clock source of the watchdog timer comes from the internal system clock. it can be enabled/disabled by set/clear wdten (bit 5 of ctrl2). for debug purpose, if the wdt reset or power low reset occur, the reset pin will be pulled low internally. the pulled - low duration due to wdt reset is about 60/fosc sec. the block diagram of the reset circuitry is shown as below. watchdog timer power-low supervisor wdten en reset logic r:100k c:0.01u external reset /reset iol=12ma @vol=0.45v
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 37 - revision a1 electrical characteristics absolute maximum ratings parame ter symbol min. max. unit dc power supply v dd - 0.3 +7.0 v input voltage v in v ss - 0.3 v dd +0.3 v input current i in - 100 +100 ma operating temperature t a 0 70 c storage temperature tst - 55 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. d.c. characteristics v dd - v ss = 5v 10%, t a = 25 c, fosc = 10 mhz, unless otherwise specified. parameter sym. specification unit test conditions min. typ. max. operating voltage v dd 4.5 5 5.5 v all function must pass! operating current i dd - - 30 ma no load, v dd = 5.5v power - down current i pd - - 100 m a no load, v dd = 5.5v input input current p2, p3.2 - p3.4, p4.0 i in1 - 75 - 10 - - - 10 +10 m a v dd = 5.5v, v in = 0v v dd = 5.5v, v in = 5.5v input current reset i in2 - 300 - 10 - - - 100 +10 m a v dd = 5.5v, v in = 0v v dd = 5.5v, v in = 5.5v input leakage current p1, p2.4 - p2.7 ( s.f. enabled) p3.0, p3.1, p3.5 - p3.7, p4.4, p4.5 h in , v in i lk - 10 - +10 m a v dd = 5.5v, 0v p reliminary w78e378/w78c378/w78 c374 - 38 - input low voltage p1, p2, p3 (except p3.0 & p3.1), p4.0, h in , v in , reset , oscin v il1 0 - 0.8 v v dd = 4.5v
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 39 - revision a1 d.c. characteristics, continued pa rameter sym. specification unit test conditions min. typ. max. input low voltage p3.0, p3.1, p4.4, p4.5 v il2 0 - 0.3 v dd v v dd = 4.5v input high voltage p1, p2, p3 (except p3.0 & p3.1), p4.0, h in , v in , reset v ih1 2.0 - v dd +0.2 v v dd = 5.5v input high voltage p3.0, p3.1, p4.4, p4.5 v ih2 0.7 v dd - v dd +0.2 v v dd = 5.5v input high voltage oscin v ih3 3.5 - v dd +0.2 v v dd = 5.5v output output low voltage p1.0, p1.1, reset v ol1 - - 0.45 v v dd = 4.5v i ol = +12 ma output low voltage p3.0, p3.1, p4.4, p4.5 v ol2 - - 0.45 v v dd = 4.5v i ol = +8 ma output low voltage p1 (except p1.0 & p1.1) p2, p3 (except p3.0 - p3.2) p4 (except p4.4 & p4.5) v ol3 - - 0.45 v v dd = 4.5v i ol = +4 ma output low voltage p3.2, oscout v ol4 - - 0.45 v v dd = 4.5v i ol = +0.8 ma output high voltage p2, p3.2 - p3.4 v oh1 2.4 - - v v dd = 4.5v i oh = - 100 m a output high voltage p4 (except p4.4 & p4.5) v oh2 2.4 - - v v dd = 4.5v i oh = - 4 ma special function output high voltage p2.0 - p2.3, p3.3, p3.4 v oh3 2.4 - - v v dd = 4.5v i oh = - 4 ma output high voltage oscout v oh4 2.4 - - v v dd = 4.5v i oh = - 3 ma notes: *1. reset has an internal pull - up resistor of about 30 k w .
p reliminary w78e378/w78c378/w78 c374 - 40 - *2. p2 and p3.2 - p3.4 can source a trans ition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. *3. p3.0, p3.1, p4.4, p4.5, h in , v in and reset are schmitt trigger inputs. appendix a. a pplication note for usage of adc to use the adc, users should pay attention to the following points: (1) according to the absolute maximum ratings, the input voltage should not exceed v dd +0.3v, especially for the adc channel pins (p2.4 - p2.7 & p3.5 - p3.7). if a voltage over v dd +0.3v exists on any of these adc channel pins, the ad conversion will fail. (2) owing to the cmos process, the adc curve of some chip might differ from those of the others. so, before using the adc, the s/w should do the adc calibrat ion described below. step 1. set (adcs2, adcs1, adcs0, adccal) = (1, 1, 1, 0) and then do ad coversion to get the adc value for the on - chip 0.948v input. suppose it is a . step 2. set (adcs2, adcs1, adcs0, adccal) = (1, 1, 1, 1) and then do ad coversion to get the adc value for the on - chip 2.924v input. suppose it is b . step 3. because the adc curve in the usable range is linear, any v and x should meet the formula: (x - a)/(v - 0.948) = (b - a)/(2.924 - 0.948) , where v is the key voltage (designed by users and thus known) and x is its predicted adc value. then, we can get x = a + (v - 0.948)(b - a)/(2.924 - 0.948) , regardless of v > 0.948v or < 0.948v. ( of course, some effort should be paid in s/w to find x .) step 4. suppose there are n keys used, the n predicted adc values for these keys can be found. 1.0 2.0 3.0 4.0 5.0 adc input voltage adc value x a b v usable range (is linear) after finding these n predicted adc values, the s/w can recognize which key is pressed by comparing the adc value of this key with the set of predicted values (found previously). ** note: to get t he exact on - chip calibration voltages (0.948v and 2.924v), the v dd should be 5.0v as close as possible.
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 41 - revision a1 test strategy before shipping: (1) vi = 0v => adc < 20 (2) vi = 0.8v => adc > 25 (3) vi = 3.2v => adc < 248 (4) vi = 4.4v => adc = 255 (5) 0.8v < vi < 3.2v, 25 points (step 0.1v) will be tested. all test points should be recognized correctly. comment: a. (1) guarantees 0v input can be recognized (adc value < 20). b. (4) guarantees 5v input can be recognized (adc value = 255). c. (2), (3) and (5) guarantee linear (with 4 bits at least) within the usable range (0.8v to 3.2v). adc value analog voltage (v) usable range 0.8 20 25 248 4.4 3.2
p reliminary w78e378/w78c378/w78 c374 - 42 - package dimensions 32 - pin p - dip 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 40 - pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2
p reliminary w78e378/w78c378/w78 c374 publication release date: december 1999 - 43 - revision a1 package dimensions, continued 44 - pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm y on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar 1. dimension d & e do not include interlead flash. 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 a b c d e h e l a a 1 2 e b 1 h d g g d e q headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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